Design and validation of the core and IOs decoupling of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors

In this paper, we present the design approach and an empirical validation of the power supply decoupling network with particular emphasis on on-die capacitance. The impact of die decoupling on core performance for the 0.18 micron version of the Pentium/spl reg/ 4 has been presented previously (T. Rahal-Arabi et al, VLSI Circ. Symp. Dig. of Tech. Papers, pp. 220-223, 2002). This paper complements the previous work by presenting the design and validation approach for the IO power supply of both the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors. As the Pentium/spl reg/ III processor has separate IO and core supplies, it is a more suitable vehicle for the IO validation. The design approach relies on using the power supply impedance model to determine the required decoupling. The model is widely used in the design of high speed systems (A. Waizman and Chee-Yee Chung, IEEE Conf. Electrical Perf. of Electron. Packaging, pp. 65-68, 2000) but this paper shows that it is less adequate to evaluate performance. The validation approach consists of building several silicon wafers of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors with various amounts of decoupling. Extensive measurements are then conducted at the silicon, package, and system levels.