A design methodology for the I/O power supply of next generation packaging

Author

Ji, Gang ; Arabi, Tawfik ; Taylor, Greg ; Beiley, Mark

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

253

Lastpage

256

Abstract

The method of three-dimensional I/O power modeling is reviewed in detail based on the learning from the previous one-dimensional and two-dimensional models. This paper covers the latest development of next generation microprocessor I/O power models and the adoption of a new three-dimensional modeling methodology to meet the challenging design requirements of a high performance signal bus with short turn-around times. The paper also presents a new technique of using damping resistors to attenuate the high frequency noise on the I/O supply.

Keywords

integrated circuit modelling; integrated circuit noise; integrated circuit packaging; interference suppression; microprocessor chips; power supply circuits; 3D I/O power modeling; HF noise attenuation; I/O power supply; damping resistors; design methodology; high frequency noise; high performance signal bus; microprocessor power models; next generation packaging; Capacitors; Circuit simulation; Design methodology; Frequency; Inductance; Microprocessors; Packaging; Power supplies; SPICE; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057926

Filename

1057926