Modeling of power supply noise in large chips with nonlinear circuits

Author

Choi, Jinseong ; Swaminathan, Madhavan ; Do, Nhon ; Master, Raj

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

257

Lastpage

260

Abstract

In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise.

Keywords

CMOS digital integrated circuits; SPICE; circuit simulation; finite difference time-domain analysis; integrated circuit modelling; integrated circuit noise; nonlinear network analysis; power supply circuits; CMOS inverter characteristics; FDTD simulation; H-tree clock network; SPICE; clock buffers; decoupling capacitances; large chips; large network simulation; linear circuits; load capacitances; nonlinear circuits; power supply noise distribution; power supply noise modelling; Capacitance; Circuit noise; Circuit simulation; Clocks; Computational modeling; Finite difference methods; Inverters; Nonlinear circuits; Power supplies; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057927

Filename

1057927