Design and application of the high-voltage ultra-shallow junction PJFET

Author

Wang, Zhikuan ; Tang, Zhaohuan ; Liu, Yong ; Shui, Guohua ; Ou, Hongqi ; Yang, Yonghui

Author_Institution

Sichuan Inst. of Solid-State Circuits, China

fYear

2010

fDate

10-11 May 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1 μm, the breakdown voltage more than 80 V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8 V~2.0 V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz^1/2, and the current noise of less than 0.05 pA/Hz^1/2.

Keywords

electric breakdown; junction gate field effect transistors; leakage currents; monolithic integrated circuits; operational amplifiers; Bi-FET; JFET compatible bipolar process; breakdown voltage; current noise; gate-leakage current; high-precision integrated OPA; high-voltage ultra-shallow junction PJFET; operational amplifier; pinch-off voltage; top-gate junction depth; voltage noise; Annealing; Breakdown voltage; Etching; ISO; Implants; Low voltage; Oxidation; Process design; Resistors; Solid state circuit design;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology (IWJT), 2010 International Workshop on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5866-0

Type

conf

DOI

10.1109/IWJT.2010.5474906

Filename

5474906