A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches

Author

Jaewoong Sim ; Loh, Gabriel H. ; Sridharan, Vilas ; O´Connor, Mike

Author_Institution

Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

34

Issue

3

fYear

2014

fDate

May-June 2014

Firstpage

80

Lastpage

90

Abstract

The resiliency problem of die-stacked memory will become important because of its lack of serviceability. This article details how to provide practical and cost-effective reliability, availability, and serviceability support for die-stacked DRAM cache architectures. The proposed approach can provide varying levels of protection, from fine-grained single-bit upsets to coarser-grained faults within the constraints of commodity non-error-correcting code DRAM stacks.

Keywords

DRAM chips; cache storage; coarser-grained faults; die-stacked DRAM cache architecture; die-stacked memory; fine-grained single-bit; non error-correcting code DRAM stacks; resiliency problem; Cache memory; Computer architecture; Decoding; Error correction codes; Organizations; Random access memory; Reliability; Cache memory; Computer architecture; DRAM; Decoding; ECC; Error correction codes; Organizations; RAS; Random access memory; Reliability; availability; cache; die stacking; error-correcting code; hardware; high performance computing; reliability; resiliency; serviceability;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2014.13

Filename

6762798