A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

Author

Sunouchi, K. ; Takato, H. ; Okabe, N. ; Yamada, T. ; Ozaki, T. ; Inoue, S. ; Hashimoto, K. ; Hieda, K. ; Nitayama, A. ; Horiguchi, F. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

23

Lastpage

26

Abstract

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 mu m/sup 2/ and a large capacitance of 30 fF using a relaxed design rule of 0.5 mu m. The cell has been fabricated and its functionality confirmed.<>

Keywords

DRAM chips; VLSI; 0.5 micron; 256 Mbit; 30 fF; 64 Mbit; DRAMs; SGT cell; bit line; capacitor electrode; intercell leakage current; matrixlike trenches; pillar silicon island; relaxed design rule; surrounding gate transistor; three-dimensional memory cell; transfer gate; Capacitance; Capacitors; Electrodes; Etching; Fabrication; Leakage current; Random access memory; Silicon; Transmission line matrix methods; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74220

Filename

74220