Special features of a VLIW architecture

This paper describes some of the special features of a very long instruction word architecture that is based on a percolation scheduling (PS) compiler. The architecture exploits fine-grain (instruction-level) parallelism in order to speed up program execution. Recent developments in low-level code transformations have been successful in exposing this parallelism. In order to take advantage of the capabilities of the PS compiler, the authors have devised a novel multi-way branch scheme that improves the overall performance of the architecture and allows speculative execution of the operations in the branch and branch delay slots. They have also adopted a modified instruction execution pipeline, which reduces the frequency of data hazards in the processor