Fabrication and performance of mesa interconnect

This paper explores the decrease in interconnect capacitance that can be achieved by the use of mesa-shaped wires. A methodology for creating mesa interconnect is described that uses simple postprocessing steps following standard CMOS IC foundry processes. By removing the oxide between metal lines and replacing it with air, the fringing capacitance between metal lines and the substrate is reduced as is the capacitance between adjacent metal lines. The decrease in capacitance resulting from the removal of the oxide between metal conductors is predicted using a 2-D electrostatic field solver and verified by measurements on test structures fabricated in an 0.5 μm HP CMOS process. Capacitance of mesa interconnect structures was reduced by roughly 40% for these test structures. For circuits dominated by interconnect capacitance, cutting the parasitic capacitance by 40% cuts the power dissipation by 40% and cuts the gate delay by 40%. Therefore the power-delay product is reduced by roughly 65% and the energy-delay product is reduced by roughly 80%. Although many issues must still be addressed to make this form of interconnect practical, the results presented in this paper suggest that the rewards in terms of decreasing capacitance could well be worth investing the effort to solve these issues