DocumentCode
2507010
Title
Advanced junction formation for sub-32nm logic devices
Author
Deshpande, S.V. ; Ozcan, A. ; Wall, D. ; Eunha Kim ; Gluschenkov, O.
Author_Institution
Semicond. R&D Center, IBM, Hopewell Junction, NY, USA
fYear
2010
fDate
10-11 May 2010
Firstpage
1
Lastpage
3
Abstract
This paper is meant to be a general overview of recent advances in new processes and process tooling (implant and anneal) for advanced junction formation. Also included are details of impact of novel implant processes, such as cold implant and pre-amorphization (PAI) implants on Nickel Silicide (NiSi) formation. We will also discuss subtle impacts of wafer temperature during ion implantation on channel stress retention and shallow junctions in today´s advanced device nodes.
Keywords
ion implantation; logic devices; semiconductor junctions; advanced junction formation; channel stress retention; cold implant; ion implantation; nickel silicide formation; pre-amorphization implants; process tooling; shallow junctions; sub-32 nm logic devices; wafer temperature; Capacitive sensors; Geometry; Germanium silicon alloys; Heating; Implants; Logic devices; Rapid thermal annealing; Silicon germanium; Silicon on insulator technology; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology (IWJT), 2010 International Workshop on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5866-0
Type
conf
DOI
10.1109/IWJT.2010.5474970
Filename
5474970
Link To Document