Component level reliability on different dimensions of lead free wafer level chip scale packages subjected to extreme temperatures

In this experiment, the thermal performance of different dimensional lead free wafer level chip scale package on laminate assemblies with SAC 305 alloys (3% Ag, 0.5%Cu) were recorded, to determine their reliability based on optimal dimensions of ball grid array, pad size and package structures. The test chips were of 6 × 6, 8 × 8 and 12 × 12 ball grid array packages with perimeter solder balls on a 0.4 mm pitch. The WLCSP assembly was subjected to high temperature accelerated life test of 1250 thermal cycles with -40°C to +125°C on a 50-minute thermal profile. The test was subjected to JEDEC JESD22-A104-B standard high and low temperature test in a single and dual zone environmental chamber to assess the solder joint performance. Reliability of the test chips was determined from the ability of components and solder interconnects to withstand the thermal stresses induced by alternating high and low temperature extremes. The SAC alloy micro structures of the components were studied in a scanning electron microscope to determine the impact of the IMCs on the solder joints. The results showed that the 6 × 6 ball grid array packages had better thermal reliability and main crack initiation position was at top right corner of the solder joints near the chip side.