Concurrency-oriented optimization for low-power asynchronous systems

Author

Plana, Luis A. ; Nowick, Steven M.

Author_Institution

Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

fYear

1996

fDate

12-14 Aug 1996

Firstpage

151

Lastpage

156

Abstract

We introduce new architectural optimizations for low-power asynchronous systems, such as Tangram-based systems of van Berkel et al. (1994). Our goal is to reduce power consumption by improving system concurrency. We introduce two new sequencer designs, with greater concurrency than existing ones, that provide the opportunity for substantial power savings through voltage scaling. To safely accommodate this added concurrency, new latch designs are presented, for both dual-rail and single-rail implementations

Keywords

CMOS logic circuits; asynchronous circuits; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; logic design; Tangram-based systems; architectural optimizations; concurrency-oriented optimization; dual-rail implementations; latch designs; low-power asynchronous systems; power consumption reduction; power savings; sequencer designs; single-rail implementations; system concurrency improvement; voltage scaling; Asynchronous circuits; Circuit synthesis; Clocks; Computer science; Concurrent computing; Design optimization; Energy consumption; Latches; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1996., International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-3571-6

Type

conf

DOI

10.1109/LPE.1996.547498

Filename

547498