DocumentCode :
2507617
Title :
Systolic architectures for computing 2-D DCT based on CORDIC techniques
Author :
Wang, Ling ; Hartimo, Iiro
Author_Institution :
Helsinki Univ. of Technol., Espoo, Finland
fYear :
1994
fDate :
12-14 Apr 1994
Firstpage :
73
Abstract :
Proposes two systolic architectures for computing 2D N×N discrete cosine transforms (DCT), which are based on the CORDIC techniques. First, it is shown that the 2D DCT can be mapped onto a systolic array directly by using row/column decomposition algorithm, where each processing element (PE) requires a ROM module of N words. Second, a new systolic algorithm using the indirect computation method is presented, in which Homer´s rule can be used. Correspondingly, the improved array has the advantage of only requiring to store two words in one ROM module of each PE. The two resulting systolic arrays are fully pipelined and composed of only two linear arrays of N CORDIC processors
Keywords :
VLSI; digital signal processing chips; discrete cosine transforms; parallel algorithms; pipeline processing; systolic arrays; 2D N×N discrete cosine transforms; CORDIC techniques; Homer´s rule; ROM module; indirect computation method; linear arrays; pipelined array; processing element; row/column decomposition algorithm; systolic algorithm; systolic architectures; Arithmetic; Computer architecture; Discrete cosine transforms; Home computing; Iterative algorithms; Read only memory; Signal processing; Silicon; Systolic arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location :
Antalya
Print_ISBN :
0-7803-1772-6
Type :
conf
DOI :
10.1109/MELCON.1994.381141
Filename :
381141
Link To Document :
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