Title :
A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
Author :
Davarik, B. ; Koburger, C.W. ; Schulz, R. ; Warnock, J.D. ; Furukawa, T. ; Jost, M. ; Taur, Y. ; Schwittek, W.G. ; DeBrosse, J.K. ; Kerbaugh, M.L. ; Mauer, J.L.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A novel planarization technique for variable size and pattern factors is presented. It is demonstrated that by the combination of reactive ion etching (RIE) and chemical mechanical polish (CMP), the process window is improved to the extent that the planarization becomes a reality. This technique is applied in the shallow trench isolation process which is used in 16-Mb DRAM (dynamic RAM) technology to achieve 0.5- mu m isolation/device dimensions. By a proper combination of RIE and CMP processes, the fundamental problem of tolerance accumulation from deposition and etchback of large film thicknesses is avoided. Excellent planarization is achieved in different areas of the DRAM chip with varying isolation sizes and pattern factors, including deep trench integration. High gate oxide breakdown yield (comparable to LOCOS isolation), which is indicative of the planarization low defect density, is demonstrated.<>
Keywords :
DRAM chips; integrated circuit technology; polishing; sputter etching; 0.5 micron; DRAM; RIE; chemical mechanical polish; deep trench integration; deposition; etchback; gate oxide breakdown yield; isolation sizes; low defect density; pattern factors; planarization technique; process window; shallow trench isolation process; tolerance accumulation; Chemical processes; Chemical technology; Electric breakdown; Etching; Isolation technology; Lithography; Planarization; Random access memory; Resists; Silicon;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74228
