Circuit techniques for low power CMOS GSI

Author

Bhavnagarwala, Azeez J. ; De, Vivek K. ; Austin, Blanca ; Mendl, J.D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1996

fDate

12-14 Aug 1996

Firstpage

193

Lastpage

196

Abstract

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60°K above room temperature

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; 0.25 micron; circuit design; low power CMOS GSI; optimization; parallel datapath; power dissipation; single datapath; static CMOS; static datapath; temperature range; CMOS technology; Circuits and systems; MOSFET circuits; Performance loss; Power MOSFET; Power dissipation; Power system modeling; Semiconductor device modeling; Temperature distribution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1996., International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-3571-6

Type

conf

DOI

10.1109/LPE.1996.547505

Filename

547505

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2508498