Interlaced accumulation programming for low power DSP

We propose a new DSP programming scheme which optimizes the program in terms of the power consumption. The optimization is to perform accumulations in an interlaced manner, which exploits our finding that the power saving by keeping a constant value at one of the inputs of a multiplier is as much as the power consumption of an entire adder or a register file of a programmable DSP. We demonstrate the power saving capability of our method by showing power simulation results for a conventional and power optimized FIR filter routine. The optimization contributes the power reduction of the data operation unit by 46% which corresponds to 19% of the chip power. This much power reduction cannot be accomplished by only improving circuit design