Hamming distance based distributed scan chain reordering for test power optimization

Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for current research. Scan chain reordering is widely used method to reduce test power. In this paper, a Hamming distance based distributed reordering for loading and unloading scan chain vector is proposed. This method focuses on how and where weighted transitions occur. In current scenario of VLSI the manufacturing cost and area of transistor is no longer a big issue for current VLSI world. In this context, the proposed method shows promising results in reduction of test power at a cost of area. The experimental results for widely sited ISCAS´89 benchmark circuits are presented to show the effectiveness of the proposed scheme.