DocumentCode :
2508972
Title :
Low-power adaptive filter architectures via strength reduction
Author :
Goel, Manish ; Shanbhag, Naresh R.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear :
1996
fDate :
12-14 Aug 1996
Firstpage :
217
Lastpage :
220
Abstract :
Low-power and high-speed algorithms and architectures for complex adaptive filters are presented in this paper. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation when applied at the algorithmic level results in a power reduction by 21% as compared to the traditional cross-coupled structure. A fine-grain pipelined architecture is then developed via the relaxed look-ahead transformation. The pipelined architecture allows high-speed operation with minimum overhead and when combined with power-supply reduction enables additional power-savings of 40-69%. Thus, an overall power-saving of 60-90% over the traditional cross-coupled architecture is achieved
Keywords :
CMOS digital integrated circuits; adaptive filters; digital filters; pipeline processing; algebraic transformations; algorithm transformations; complex adaptive filters; fine-grain pipelined architecture; high-speed algorithms; high-speed operation; low-power adaptive filter architectures; power reduction; power-savings; power-supply reduction; relaxed look-ahead transformation; strength reduction transformation; Adaptive filters; Adders; Algorithm design and analysis; Circuits; Computer architecture; Electronic mail; Power dissipation; Technological innovation; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
Type :
conf
DOI :
10.1109/LPE.1996.547511
Filename :
547511
Link To Document :
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