Double-Pole Four-Throw RF CMOS switch design with double-gate transistors

In this paper, we have explored the design features of a Double-Pole Four-Throw (DP4T) RF CMOS switch with use of a novel Vertical Slit Field Effect Transistor (VSFET). This proposed switch circuit uses the double-gate which minimizes the number of transistors and increases the logic density of the transistor per unit area as compare to simple switch. These double gates are independently controlled. This will provide a switch with a drive circuit that free from signal propagation delay and additional voltage power supply. Further, main objective is to provide a plurality of such switches arranged in a densely configured switch array, where the power and circuit area is reduced as compared to a tied gate configuration.