Ultra low-voltage and high speed dynamic and static CMOS precharge logic

Author

Berg, Y. ; Mirmotahari, O.

Author_Institution

Inst. of Technol., Vestfold Univ. Coll., Horten, Norway

fYear

2012

fDate

6-8 June 2012

Firstpage

1

Lastpage

4

Abstract

In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process.

Keywords

CMOS logic circuits; Monte Carlo methods; SPICE; high-speed integrated circuits; logic gates; low-power electronics; HSpice; Monte Carlo simulation; TSMC process; ULV logic; high speed dynamic CMOS precharge logic; high speed static CMOS precharge logic; inverter delay; low power inverter; process parameter; size 90 nm; standard CMOS inverter; standard CMOS logic; supply voltage; ultra low voltage domino inverter; voltage 200 mV to 400 mV; CMOS integrated circuits; Delay; Inverters; Logic gates; MOS devices; Standards; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2012 IEEE

Conference_Location

Paris

Print_ISBN

978-1-4673-0822-9

Type

conf

DOI

10.1109/FTFC.2012.6231718

Filename

6231718