Increment/decrement/2´s complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2´s complement etc. This paper presents an architecture which can perform increment/decrement/2´s complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.