Power-aware automated hybrid pipelining of combinational circuits

Hybrid pipelining can help us achieve faster clock rates by combining the advantages of both flop and wave pipelining and has signal processing applications. In this paper we formulate this problem for acyclic combinational circuits as a mixed integer non linear programming (MINLP) problem and give three algorithms to obtain good solutions. The first method is a sensitivity based approach. The second method uses geometric programming (GP) that works well for smaller circuits. The third method uses a novel technique towards level based delay propagation model using GP. The algorithms are tested on ISCAS-85 benchmark circuits and combinational circuits generated by a method developed by us and compared for speed and efficiency. Our experimental observations show the existence of a minimum supply voltage and a threshold voltage at which the circuits generated have less latency and power consumption.