Statistical leakage estimation in 32nm CMOS considering cells correlations

In this paper a method to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations is proposed. The statistical leakage estimation is based on a pre characterization of library cells considering correlations (ρ) between cells leakages. A method to create cells leakage correlation matrix is introduced. The maximum relative error achieved in the correlation matrix is 0.4% with respect to the correlations obtained by Monte Carlo simulations. The total circuit leakage is calculated using this correlation matrix along with the mean (μ), and variance (σ²) of each cell leakage. This approach is used for standby leakage estimation in 32nm technology. The accuracy and efficiency of the approach is demonstrated on a C3540 (8 bit ALU) ISCAS85 Benchmark circuit.