DocumentCode :
2509423
Title :
High-level power estimation and the area complexity of Boolean functions
Author :
Nemani, Mahadevamurty ; Najm, Farid N.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear :
1996
fDate :
12-14 Aug 1996
Firstpage :
329
Lastpage :
334
Abstract :
Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (RTL). This paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model to estimate the area based on a new complexity measure called the average cube complexity. This model has been implemented, and empirical results demonstrating its feasibility and utility are presented
Keywords :
Boolean functions; circuit optimisation; computational complexity; delays; high level synthesis; logic CAD; area complexity; average cube complexity; complexity measure; high-level power estimation; register transfer level; single-output Boolean functions; Area measurement; Boolean functions; Capacitance measurement; Circuits; Design automation; Libraries; Power dissipation; Predictive models; Process design; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
Type :
conf
DOI :
10.1109/LPE.1996.547534
Filename :
547534
Link To Document :
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