Low power and robust ground gated memory banks with combined write assist techniques

Asymmetrically ground-gated seven-transistor (7T) static random access memory (SRAM) cells are presented in this paper for providing a low leakage data preserving SLEEP mode with strong data stability characteristics. Combined write assist techniques are utilized to enhance the write ability of the 7T SRAM cells. The write margin is enhanced by up to 2.75× and the write delay is reduced by up to 71.70% as compared to a previously published asymmetrically ground-gated 7T SRAM circuit. Furthermore, the new ground-gated 7T memory circuit enhances the data stability by 2.11× and reduces the leakage power consumption by 65.38% as compared to a ground-gated memory array with conventional 6T SRAM cells. The design tradeoffs and options of asymmetrically ground-gated 7T SRAM circuits are evaluated with a TSMC 65nm multi-threshold voltage CMOS technology.