Title :
Comparison of high speed voltage-scaled conventional and adiabatic circuits
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
The power versus frequency performance of a micro-pipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Using a circuit simulator, the supplies and operating voltages of each family are optimized for minimum power consumption at each frequency. One of the energy-recovering logic families is shown to be capable of substantially lower dissipation than the conventional case, one is comparable, and one is worse
Keywords :
CMOS logic circuits; circuit analysis computing; integrated circuit design; logic CAD; pipeline processing; circuit simulator; micro-pipelined conventional CMOS logic family; minimum power consumption; operating voltages; pipelined energy-recovering logic families; power dissipation; voltage-scaled adiabatic circuits; Adders; CMOS logic circuits; Circuit simulation; Clocks; Frequency; Logic circuits; Logic gates; MOS devices; Switching circuits; Voltage;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547542
