Title :
Ultra low voltage ΔΣ modulation using biased inverters in 130nm CMOS
Author :
Michel, Fridolin ; Steyaert, Michiel
Author_Institution :
Dept. Elektrotech. ESAT-MICAS, K.U. Leuven, Leuven, Belgium
Abstract :
The design challenges of an ultra low voltage ΔΣ modulator are discussed, which encompasses a switched capacitor technique for efficient biasing of inverter-based integrators, an ultra low voltage comparator as well as efficient on-chip bias current generation and clock boosting for fast switching transients. All building blocks run at a supply voltage of only 250 mV while providing 61 dB SNDR in 10 kHz bandwidth at a total power consumption of 7.5 μW.
Keywords :
CMOS integrated circuits; clocks; comparators (circuits); delta-sigma modulation; integrating circuits; invertors; low-power electronics; switched capacitor networks; CMOS; SNDR; bandwidth 10 kHz; biased inverter; clock boosting; inverter-based integrator; noise figure 61 dB; on-chip bias current generation; power 7.5 muW; size 130 nm; switched capacitor; switching transient; ultra low voltage ΔΣ modulation; ultra low voltage comparator; voltage 250 mV; Capacitors; Clocks; Inverters; Logic gates; Low voltage; Modulation; Switches;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2012 IEEE
Conference_Location :
Paris
Print_ISBN :
978-1-4673-0822-9
DOI :
10.1109/FTFC.2012.6231739
