DocumentCode :
2509717
Title :
Design and implementation of a parallel Verilog simulator: PVSim
Author :
Li, Tun ; Guo, Yang ; Li, Si-Kun
Author_Institution :
Nat. Univ. of Defense Technol., Changsha, China
fYear :
2004
fDate :
2004
Firstpage :
329
Lastpage :
334
Abstract :
Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design. This paper presents a parallel Verilog simulator-PVSim, which bases on optimistic asynchronous parallel simulation algorithm and MPI library. A new module-based simulation component mapping method is proposed. And an efficient module-based partition algorithm combined with pre-simulation partition algorithm is adopted. This paper introduces the architecture of PVSim, the Verilog component mapping techniques, the distributed simulation cycle arrangement and the circuit partition algorithm in detail. Experimental results show that PVSim can get promising speedup, as well as distributed workload and communication cost across processors.
Keywords :
Unix; VLSI; hardware description languages; integrated circuit design; message passing; time warp simulation; MPI library; PVSim; VLSI system design; Verilog component mapping techniques; circuit partition algorithm; distributed simulation cycle; module based partition algorithm; module based simulation component mapping; optimistic asynchronous parallel simulation algorithm; parallel HDL simulation; parallel Verilog simulator design; presimulation partition algorithm; Algorithm design and analysis; Circuit simulation; Costs; Digital systems; Discrete event simulation; Hardware design languages; Partitioning algorithms; Process design; System recovery; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1260944
Filename :
1260944
Link To Document :
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