Design for verification with System Verilog

Design for verification in the EDA industry is currently going through a paradigm shift due to the relentless growing problem of verifying large complex systems. A major impact in solving this problem has been the development and standardization of significant set of enhancements to the Verilog language under the name of System Verilog. This talk will review several aspects of this new language and how they form a critical part in the new design for verification paradigm.