The properties and annealing of gate oxide damage of oxynitride-passivated CMOS transistors arising from mechanical stresses during packaging

The effects of the dicing and packaging of oxynitride-passivated CMOS devices are reported. It is shown that the dicing leads to extremely large threshold voltage shifts for both n- and p-MOS devices. The damage can mostly be annealed away at high temperatures, although the time and temperature are critical. Interface states and oxide charges are shown to be created and to follow different annealing kinetics. It is found that, even after full annealing, there is an increased hot-carrier susceptibility. No such effect is found for oxide and nitride passivations. Furthermore, the threshold voltage shift of a device is found to depend on its proximity to the point of dicing, indicating that mechanical stress is at the origin of this effect.<>