Efficient implementation of fast convolution in ASIP

In this paper various approaches of implementing a hardware efficient fast convolution have been discussed. Long length convolutions implemented on a FPGA are not area, power efficient and also it cannot be implemented on a single FPGA. To increase the speed of long convolutions and to meet the calculation capacity of each single FPGA chip, the long coefficient sequence can be partitioned into short sub-sequences. Each short length convolution can then be made area efficient at the expense of decrease in speed by implementing them as a convolution ASIP. The asynchronous ASIP is still faster than a synchronous ASIP. The speed of an asynchronous convolution processor can be further increased by applying Algorithmic Strength Reduction (ASR) where the number of multiplications, (which is more time consuming than an addition) is alleviated at the expense of increase in the number of additions required in a convolution process. Several algorithms based on ASR which would lead to a faster convolution ASIP have been discussed.