Parallel multi-context architecture with high-speed synchronization mechanism

Current interest in parallel processing architecture is focused on compatibility of extracting parallelism and improving processor utilisation. The authors propose a new parallel processing architecture called CODA which can attain a high processor utilization while extracting parallelism effectively. CODA is based on single-thread pipeline architecture with advanced instruction fetch, which uses processors efficiently. Synchronization can be performed implicitly at a register reading to provide high-speed fine-grain synchronization effectively. CODA also has a hardware multi-context support which reduces the cost of context switch caused by synchronization. Synchronization and packet communication ability are effectively integrated into an execution pipeline by an instruction insertion mechanism