DocumentCode
2510657
Title
Design optimization of CMOS CDC comparators
Author
Wang, Mingzhen ; Xue, Hongxi ; Yang, Gang ; Wu, Yingjian
Author_Institution
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2011
fDate
21-23 Oct. 2011
Firstpage
139
Lastpage
144
Abstract
This paper presents design of CMOS CDC-based comparators with an optimum method to suppress dynamic offset for high-speed flash ADCs. The CDC-based comparators are introduced, analyzed, modeled and optimized. The experiment results have verified the design optimization. Compared to the ADCs with random sizing CDC comparators, the dynamic performance in terms of SNR and SFDR has improved over 30% @ the signal frequency lower than 800MHz and over 140% @ the signal frequency higher than 800MHz.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; circuit optimisation; clocks; comparators (circuits); high-speed integrated circuits; integrated circuit design; CMOS CDC comparator design optimization; SFDR; SNR; clocked digital comparator; dynamic offset suppression; high-speed flash ADC; spurious-free dynamic range; Capacitance; Inverters; Mathematical model; Quantization; Switches; Threshold voltage; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Problem-Solving (ICCP), 2011 International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4577-0602-8
Electronic_ISBN
978-1-4577-0601-1
Type
conf
DOI
10.1109/ICCPS.2011.6092215
Filename
6092215
Link To Document