Carry circuitry for LUT-based FPGA

This paper presents a carry chain design optimized for implementing multipliers along with the adder circuitry. This kind of architecture will be very useful for designs which have very large number of mathematical operations in it. The aim of the architecture is to accommodate as much logic as possible in one LUT without increasing the size of the LUT proportionately. The discussed carry chain design is compatible with both 3-input as well as 4-input LUTs. The paper ends with a comparative study of multiplier implementation on various popular FPGA architectures.