• DocumentCode
    2511125
  • Title

    On interconnecting circuits with multiple scan chains for improved test data compression

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2004
  • fDate
    2004
  • Firstpage
    741
  • Lastpage
    744
  • Abstract
    We show that when a scan design consists of interconnected circuits, test data volume reductions can be achieved by connecting the scan chains of adjacent circuits appropriately. We formulate this problem as a problem of finding a permutation of the scan chains of one circuit with respect to another so as to minimize the number of different scan vectors required for testing both circuits. We propose a procedure for solving this problem, and present experimental results.
  • Keywords
    circuit testing; data compression; vectors; circuit testing; interconnected circuits; multiple scan chains; permutation finding; scan design; scan vector minimization; test data compression; test data volume reductions; Circuit testing; Cities and towns; Design methodology; Encoding; Hardware; Integrated circuit interconnections; Joining processes; Test data compression; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2004. Proceedings. 17th International Conference on
  • Print_ISBN
    0-7695-2072-3
  • Type

    conf

  • DOI
    10.1109/ICVD.2004.1261016
  • Filename
    1261016