• DocumentCode
    2511279
  • Title

    An efficient method to generate test vectors for combinational cell verification

  • Author

    Patel, Nirav ; Srihari, M. ; Maheswari, Pooja ; Nandakumar, G.N.

  • fYear
    2004
  • fDate
    2004
  • Firstpage
    769
  • Lastpage
    772
  • Abstract
    In library cell verification, functionality and timing of each cell needs to be verified. Generation of an optimal and exhaustive test stimuli for each cell is a challenging problem. Though formal verification techniques are available today, vector based verification is still practiced in the industry. Here we introduce an efficient method to generate test vectors for the verification of combinational cells. The method proposed is based on the extended Gray-code concept. Generated test vectors cover all possible Single Input Change (SIC) transitions without any redundancy. An optimal implementation scheme, in terms of performance and memory, is also proposed.
  • Keywords
    Gray codes; formal verification; Gray codes; combinational cell verification; formal verification techniques; library cell verification; single input change transitions; test vector generation; vector based verification; Buildings; Formal verification; Hardware design languages; Libraries; Optimization methods; Reflective binary codes; Silicon carbide; Testing; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2004. Proceedings. 17th International Conference on
  • Print_ISBN
    0-7695-2072-3
  • Type

    conf

  • DOI
    10.1109/ICVD.2004.1261023
  • Filename
    1261023