RTL modeling and simulation using JAVA

This paper presents a JAVA based framework for RTL modeling and simulation of digital hardware designs. After linking between object-oriented concepts and RTL models, the JAVA analogy to features found in a widely used hardware description language like Verilog is laid down. While focusing primarily on synchronous designs and cycle based simulation, the way to broaden this scope to event driven simulation is pointed out. Using a general object-oriented programming language for RTL modeling and simulation paves way for a more seamless software and hardware integration of a typical digital system.