Title :
FPGA implementation of vedic floating point multiplier
Author :
Kodali, Ravi Kishore ; Boppana, Lakshmi ; Yenamachintala, Sai Sourabh
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Warangal, Warangal, India
Abstract :
Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.
Keywords :
field programmable gate arrays; floating point arithmetic; IEEE-754 based Vedic multiplier; Urdhva tiryakbhyam sutra; Xilinx FPGA; vedic floating point multiplier; Algorithm design and analysis; Computers; Delay effects; Digital signal processing; Field programmable gate arrays; Signal processing algorithms; FPGA; Floating Point; Vedic multiplication;
Conference_Titel :
Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015 IEEE International Conference on
Conference_Location :
Kozhikode
DOI :
10.1109/SPICES.2015.7091534