DocumentCode
2511568
Title
High-performance power grids for nanometer technologies
Author
Sapatnekar, Sachin S.
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
2004
fDate
2004
Firstpage
839
Lastpage
844
Abstract
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of recent techniques for the analysis and optimization of supply networks, and discusses future trends in power grid design.
Keywords
circuit optimisation; integrated circuit noise; nanotechnology; nanometer technologies; onchip noise sources; power grids; shrinking noise margins; supply network optimization; Circuit noise; Conductors; Equations; Noise reduction; Packaging; Pins; Power grids; Power system modeling; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN
0-7695-2072-3
Type
conf
DOI
10.1109/ICVD.2004.1261036
Filename
1261036
Link To Document