DocumentCode
2511938
Title
Floorplan classification algorithms
Author
Gao, Kun ; Mehta, Dinesh P.
Author_Institution
Dept. of Math. & Comput. Sci., Colorado Sch. of Mines, CO, USA
fYear
2004
fDate
2004
Firstpage
975
Lastpage
980
Abstract
We present optimal linear time algorithms that determine whether a given general floorplan represented by a q-sequence or twin binary trees is slicing or hierarchical. Experimental results on several benchmarks are presented.
Keywords
binary sequences; circuit optimisation; integrated circuit layout; trees (mathematics); benchmarks; circuit optimisation; floorplan classification algorithms; optimal linear time algorithms; q-sequence; twin binary trees; Binary sequences; Binary trees; Circuit simulation; Computational modeling; Design automation; Polynomials; Process design; Simulated annealing; State-space methods; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN
0-7695-2072-3
Type
conf
DOI
10.1109/ICVD.2004.1261057
Filename
1261057
Link To Document