Design of a Novel Power-on-Reset Circuit Based on Power Supply Detector

Author

Zhang, Jin ; Jiang, Lin ; Zeng, Zecang

Author_Institution

Dept. of Comput. Sci. & Technol., Xi´´an Univ. of Posts & Telecommun., Xi´´an, China

fYear

2009

fDate

25-27 Sept. 2009

Firstpage

355

Lastpage

359

Abstract

A power-on-reset circuit of novel simple structure and high reliability is proposed. The circuit has been designed in 0.5 mum bipolar CMOS technology. The simulation was performed with 0.5 mum CSMC process model and Cadence Spectre and the results show that the circuit has a stable and reliable performance. With the differences of supply voltage´s ramp rate, temperature and process, the change of threshold voltage is in small distribution.

Keywords

CMOS integrated circuits; bipolar integrated circuits; integrated circuit reliability; power supply circuits; CSMC process model; Cadence Spectre; bipolar CMOS technology; circuit reliability; power supply detector; power-on-reset circuit design; size 0.5 mum; supply voltage ramp rate; CMOS technology; Capacitors; Circuit simulation; Delay; Detectors; Diodes; Embedded computing; Power supplies; Temperature; Threshold voltage; BiCMOS technology; Power-on-Reset; power supply detector; temperature coefficient; threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Scalable Computing and Communications; Eighth International Conference on Embedded Computing, 2009. SCALCOM-EMBEDDEDCOM'09. International Conference on

Conference_Location

Dalian

Print_ISBN

978-0-7695-3825-9

Type

conf

DOI

10.1109/EmbeddedCom-ScalCom.2009.70

Filename

5341650