DocumentCode
2512146
Title
A built-in-self-test scheme for digital to analog converters
Author
Sunil Rafeeque, K.P. ; Vasudevan, Vinita
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
fYear
2004
fDate
2004
Firstpage
1027
Lastpage
1032
Abstract
This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in digital to analog converters (DACs). The BIST scheme measures each transition and estimates non-linearity errors. It makes use of a sample and subtract circuit and a VCO. The circuit is designed using 0.35 μm CMOS technology from AMS. The simulation results are included in this paper. Errors estimated using the BIST scheme simulation match well with measured errors.
Keywords
CMOS integrated circuits; built-in self test; digital-analogue conversion; integrated circuit design; sample and hold circuits; voltage-controlled oscillators; 0.35 micron; BIST; CMOS technology; DAC; VCO; built in self test; digital-analog converters; integrated circuit design; sample circuit; static nonlinearity errors; subtract circuit; voltage controlled oscillators; Built-in self-test; CMOS technology; Clocks; Counting circuits; Digital-analog conversion; Frequency measurement; Linearity; Testing; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN
0-7695-2072-3
Type
conf
DOI
10.1109/ICVD.2004.1261065
Filename
1261065
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