Title :
A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation
Author :
Seth, Kavish ; Rangarajan, P. ; Srinivasan, S. ; Kamakoti, V. ; Kuteshwar, V. Bala
Author_Institution :
Atheros India LLC, India
Abstract :
This paper describes a fully pipelined parallel architecture for the New Three Step Search (NTSS) hierarchical search block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces efficient solution for real-time motion estimation required in video applications with low memory bandwidth requirement. This architecture is the best tradeoff in terms of hardware overload and speed among the all-existing Three Step Search (TSS) architectures and is also suitable for estimation of small motion in video coding. This architecture can be used for various video applications from low bit-rate video to HDTV systems.
Keywords :
high definition television; motion estimation; parallel architectures; search problems; video coding; HDTV systems; block motion estimation; high definition television; low bit rate video; low memory bandwidth requirement; new three step search algorithm; pipelined parallel architecture; real-time motion estimation; search block-matching algorithm; video coding; Bandwidth; Computer architecture; HDTV; Hardware; Image sequences; Motion estimation; Parallel architectures; Scheduling algorithm; Very large scale integration; Video coding;
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
DOI :
10.1109/ICVD.2004.1261071