DocumentCode :
2512497
Title :
Thermal enhancement methods for ECL gate array packaging
Author :
Huang, C.C. ; Sharma, N.K.
Author_Institution :
Nat. Semicond. Inc., Milpitas, CA, USA
fYear :
1988
fDate :
10-12 Feb 1988
Firstpage :
78
Lastpage :
83
Abstract :
Three different approaches used for thermal conductivity enhancement of emitter-coupled logic (ECL) gate array packaging are described. The approaches presented are: material substitution; package modification; and process modification. The method of thermal resistance measurement, the methods and process of modification of packaging, and the results of measurement are also described. Material substitution consisted of replacing the electrically conducting Cu-W alloy substrate with high thermal conductivity, electrically insulating inserts of BeO/AIN. This approach, though successful in achieving desired thermal enhancements, was not cost effective. Package modification together with process modification was needed to produce packages with thermal resistance less than 1° C/W and natural convection of less than 3° C/W at 1000 ft/min. Data at various air speeds from 250 to 1000 ft/min are presented for various thermal enhancement methods
Keywords :
emitter-coupled logic; heat sinks; integrated logic circuits; packaging; thermal resistance measurement; BeO-AlN; ECL gate array packaging; cost; natural convection; thermal enhancement; thermal resistance measurement; Conducting materials; Costs; Dielectrics and electrical insulation; Electric resistance; Electrical resistance measurement; Logic arrays; Logic gates; Packaging; Thermal conductivity; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal and Temperature Measurement Symposium, 1988. SEMI-THERM IV., Fourth Annual IEEE
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/SEMTHE.1988.10601
Filename :
10601
Link To Document :
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