DocumentCode :
2512574
Title :
A Scheduler Support Unit for Reactive Microprocessors
Author :
Salcic, Zoran ; Gruian, Flavius ; Roop, Partha ; Wahid, Alif
Author_Institution :
Dept. of Electr. & Comput. Eng., Auckland Univ.
fYear :
0
fDate :
0-0 0
Firstpage :
368
Lastpage :
372
Abstract :
Efficient scheduling mechanisms are essential for implementing real-time operating systems on embedded microprocessors. Reactive processors provide mechanisms and an instruction set architecture more suitable for dealing with external signals than it is the case with traditional interrupts. By extending the reactive framework further we demonstrate simple and efficient hardware-implemented scheduling of tasks with static priorities. The scheduler support unit is added to the reactive microprocessor core. The real-time scheduler shows substantial improvement of performance over the conventional approach of using prioritized interrupts
Keywords :
instruction sets; microprocessor chips; operating systems (computers); processor scheduling; real-time systems; embedded microprocessor; instruction set architecture; reactive microprocessor; real-time operating system; scheduler support unit; scheduling mechanism; Delay; Dynamic scheduling; Hardware; Microprocessors; Operating systems; Parallel processing; Pipelines; Processor scheduling; Real time systems; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded and Real-Time Computing Systems and Applications, 2006. Proceedings. 12th IEEE International Conference on
Conference_Location :
Sydney, Qld.
ISSN :
1533-2306
Print_ISBN :
0-7695-2676-4
Type :
conf
DOI :
10.1109/RTCSA.2006.9
Filename :
1691336
Link To Document :
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