Escape routing from chip scale packages

Electronic packaging has steadily been miniaturized to reduce component weight and volume for portable applications and to enhance system speed performance. Package sizes approach the chip size in the chip size package (CSP) while retaining discrete package advantages in handling and test. In the CSP approach the ball interconnect (C5 balls) between package and mother board may be placed at pitches as low as 0.5 mm. There are, however, limitations to the number of escape vias/traces which mother boards can handle. These limits are a function of the C5 pad size and pitch, via land size and pitch, trace pitch and the number of C5 pads. In addition, features such as blind and buried vias can enhance the under-package escape routability but for PWBs these features bring a significant board cost penalty. This paper addresses escape layer count for full array CSPs and also depopulated array CSPs where C5 pads are only in outer C5 rings. For a full C5 array, using high density (0.5 mm) C5 pitch and leading edge PWB technology for the mother board (projected for the year 2000), only one signal ring can escape per PWB layer. The inner, smaller rings in this calculation with ~30% power and ground are routed to common power and ground planes. In order to succeed in full array escape within the PWB, the costly add-ons of filled, blind vias are required. With emerging high density interconnect (HDI) where via pads are in the range of 0.2 mm or less and trace pitch is about 0.1 mm, escape routing is readily achieved