DocumentCode :
2513534
Title :
Efficient Scratchpad Memory Management Based on Multi-thread for MPSoC Architecture
Author :
Hu, Wei ; Wang, Gang ; Chen, Jian ; Lou, Xueqing ; Chen, Tianzhou
Author_Institution :
Coll. of Comput. Sci., Zhejiang Univ., Hangzhou, China
fYear :
2009
fDate :
25-27 Sept. 2009
Firstpage :
429
Lastpage :
434
Abstract :
Scratchpad memory (SPM) is software-controlled on-chip memory with shorter access time and lower power consumption compared with cache. SPM is used increasingly widespread to meet the strict requirements on performance, power consumption and design cost of the embedded systems. This paper presents an efficient SPM management based on multi-thread for multiprocessor system on chip (MPSoC) architecture, which is the popular in embedded processors. The proposed mechanism is composed of: (1) processor core groups; (2) SPM primitives; (3) SPM based multi-thread scheduling. The experimental results show that the proposed mechanism can improve the performance of the system with lower power consumption.
Keywords :
microprocessor chips; multi-threading; processor scheduling; storage management; storage management chips; system-on-chip; MPSoC architecture; SPM management; embedded system; multiprocessor system; multithread scheduling; power consumption; scratchpad memory management; software-controlled on-chip memory; Embedded computing; Embedded system; Energy consumption; Energy management; Memory management; Power system management; Processor scheduling; Scanning probe microscopy; System-on-a-chip; Yarn; MPSoC; Scratchpad memroy; embedded system;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Scalable Computing and Communications; Eighth International Conference on Embedded Computing, 2009. SCALCOM-EMBEDDEDCOM'09. International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-0-7695-3825-9
Type :
conf
DOI :
10.1109/EmbeddedCom-ScalCom.2009.83
Filename :
5341736
Link To Document :
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