An efficient design of FSM based 32-bit unsigned high-speed pipelined multiplier using Verilog HDL

This paper shows a new methodology to design hardware of 32-bit unsigned pipelined multiplier. The proposed hardware design is based on Finite State Machine (FSM) for reducing hardware resources and proliferating maximum frequency. Our suggested pipelined multiplier design contains only four 40-bit full adders to complete 64-bit 32 partial products addition. The synthesis report of the 32-bit pipelined multiplier shows that the usage of the logical resources of FPGA is significantly less than the earlier 32-bit multiplier design. Moreover, the proposed pipelined multiplier hardware doesn´t use any DSP or dedicated multiplier block of FPGA for the multiplication process. So, our proposed design is technology independent and it gives uttermost performance both in FPGA and ASIC. The maximum frequency achieved for operation latency of 9-clock cycle is 326.243 MHz for computing 32-bit×32-bit unsigned multiplication and the pipelined multiplier hardware design is tested on Xilinx Virtex-6 XC6VLX75T-3-FF484 FPGA.