Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning

System-on-a-chip (SOC) uses embedded cores those require a test architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach may also be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). This paper presents an algorithm for minimizing the post bond test time for 3D core-based SOCs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into two groups and places the cores of these groups in two layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.