A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design

In this paper, we propose a new designated clock generation and distribution (DCGD) chip scheme to offer extremely low jitter clock delivery. The proposed scheme is especially suitable for 3-D multi-stack SiP applications. Considerably enhanced timing jitter performance of the proposed scheme is enabled by the help of sufficiently improved simultaneous switching noise (SSN) isolation from the digital blocks and by lowered inductive parasitics of the clock distribution networks. Substantial suppression of the timing jitter under a severe SSN environment was well proved through a series of design, fabrication, and measurement process of test devices and packages.