Squaring in reversible logic using iterative structure

Digital multipliers are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. But the implementation of squaring has the advantage that we can avoid the generation of many partial products used in multipliers by eliminating the redundant bits, thus resulting the circuit to be simpler with less hardware, propagation delay and power consumption. Our work proposes two designs of dedicated squaring techniques in reversible circuits. We use the recursion to achieve our design. The design for n bits is recursively obtained by appending some extra circuitry with the design for (n-1) bits. Our techniques make optimum use of ancillary inputs, garbage outputs and quantum cost and compare favourably with the recent work [1] in this area. Both the designs are having modular structures and can be systemically designed.